This invention relates generally to error correcting apparatus for correcting errors in digital data, and more particularly the invention relates to apparatus for correcting errors in digital video disk (DVD) formatted data.
Digital data typically has an error code associated with bytes (8 bits) of data for error check and correction. DVD data in an ECC block configuration has a unique data structure in which bytes (16 bits per byte) are stored in 208 rows with 182 columns. See FIG. 1. Each row has 10 check bytes for inside parity (PI). Therefore, 10 columns of the 182 are dedicated to check bytes. Similarly, 16 rows are provided for check bytes for outside parity (PO) with the 16 rows being interleaved with 192 data rows or one row of check bytes after each 12 data rows.
Received DVD data must be checked for errors and corrected before storage for later use. FIG. 2 is a functional block diagram of DVD error correction apparatus in accordance with the prior art. As shown, input data is fed directly to a dram 10 and to a Pi engine 12 which corrects errors based on PI check bytes and the corrected bytes are written to DRAM. The PI corrected data from DRAM 10 is then read by the PO engine 14 which generates syndromes for PO correction bytes and are written back to DRAM 10 and correction is done based on the outside parity (PO) bytes. Thus, in accordance with the prior art a large DRAM 10 must be provided for storing all of the partially corrected data, and then the partially corrected data must be retrieved from DRAM 10 for use by the PO engine. Thereafter, the PO corrected data is reapplied to DRAM 10 for storage. Since PO calculations are based on columns, burst accesses are reduced and thereby speed is reduced. This architecture can support only a maximum data rate of 8 times the DVD speed and this requires very fast SDRAMS or DRAMS and the synthesizing to high frequency. One alternative would be to use huge internal SRAMS (37-74 Kbytes) or even more but this would be a costly solution. Further, since higher speeds like 16xc3x97 and above with less cost will be required in the future, and new architecture is required.
In accordance with the invention, accesses to processed data in SDRAM memory for PO error correction is minimized by employing a scratch pad SRAM memory for storing syndromes calculated by the PO engine which are later used to further correct the processed data after all rows of data are read and PO syndromes are calculated. The PO engine can then identify incorrect data from the syndromes and correct the stored processed data on a random basis.
More particularly, the PO syndromes can be calculated for columns of PI processed data as the PI corrections are being made on rows of DVD data in an ECC block. Unlike the prior art, the PI engine and the PO engine can be operating concurrently on data from the same ECC block.
In a preferred embodiment, 8K SRAM memory is used for the scratch pad internal memory for the PO engine thereby reducing costs. SDRAMs are used for storing the processed data, this architecture is expandable to higher speeds, and more error correction capability can be introduced with the implementation of reiterative error correction.